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authorJiansong Chen <[email protected]>2020-07-21 12:21:40 +0800
committerAlex Deucher <[email protected]>2020-07-21 15:37:40 -0400
commit9c0551f23e653e848681d651603e3122e18a1c65 (patch)
tree404cefa3f28bb2e60cf92865b6b790bae3bd8c4e
parent4908d02637b34e604efbe77aadecb510338d92c9 (diff)
drm/amd/powerplay: fix typos for clk map
It should be DCLK1->PPCLK_DCLK_1 and VCLK->PPCLK_VCLK_0. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Likun Gao <[email protected]> Acked-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
-rw-r--r--drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index cae8e776fafe..87eedd7c28ec 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -128,8 +128,8 @@ static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
CLK_MAP(UCLK, PPCLK_UCLK),
CLK_MAP(MCLK, PPCLK_UCLK),
CLK_MAP(DCLK, PPCLK_DCLK_0),
- CLK_MAP(DCLK1, PPCLK_DCLK_0),
- CLK_MAP(VCLK, PPCLK_VCLK_1),
+ CLK_MAP(DCLK1, PPCLK_DCLK_1),
+ CLK_MAP(VCLK, PPCLK_VCLK_0),
CLK_MAP(VCLK1, PPCLK_VCLK_1),
CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
CLK_MAP(DISPCLK, PPCLK_DISPCLK),