diff options
| author | Biju Das <[email protected]> | 2023-04-11 11:03:41 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <[email protected]> | 2023-05-08 09:16:45 +0200 |
| commit | 9af677e0747965f30b6c3540d464d34e22da5336 (patch) | |
| tree | 71455ee0f38bd23627413da64676fbe1abce803f | |
| parent | fad741768e7b9572fad05fe4523c76a236c4056a (diff) | |
arm64: dts: renesas: r9a07g044: Add vspd node
Add vspd node to RZ/G2L SoC DTSI.
Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index dd98688c3661..796ad2034699 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -697,6 +697,19 @@ }; }; + vspd: vsp@10870000 { + compatible = "renesas,r9a07g044-vsp2"; + reg = <0 0x10870000 0 0x10000>; + interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>, + <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>, + <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_LCDC_RESET_N>; + renesas,fcp = <&fcpvd>; + }; + fcpvd: fcp@10880000 { compatible = "renesas,r9a07g044-fcpvd", "renesas,fcpv"; |