diff options
| author | AngeloGioacchino Del Regno <[email protected]> | 2024-04-09 13:42:10 +0200 |
|---|---|---|
| committer | AngeloGioacchino Del Regno <[email protected]> | 2024-06-27 10:10:20 +0200 |
| commit | 9af42385908bb4c33adf9f39af51ba269dbf9882 (patch) | |
| tree | b3b0b00dc04a5a12365698da36f2149ebf1ada43 | |
| parent | 048a70e3141a660d116bb86fe7e158235a9c4656 (diff) | |
arm64: dts: mediatek: mt8395-nio-12l: Enable PHYs and USB role switch
Enable the PCIe0 PHY to be able to set calibrations read from eFuses,
improving the stability and performance of the PCIe link.
While at it, also enable the T-PHYs for both PCIe1 and for USB, allowing
the USB ports to finally switch to gadget mode if needed, and configure
the VBUS/ID pins of both USB ports for the same.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts index abd6612b8624..dfd0cbd71607 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts @@ -685,6 +685,26 @@ }; }; + usb3_port0_pins: usb3p0-default-pins { + pins-vbus { + pinmux = <PINMUX_GPIO63__FUNC_VBUSVALID>; + input-enable; + }; + }; + + usb2_port0_pins: usb2p0-default-pins { + pins-iddig { + pinmux = <PINMUX_GPIO130__FUNC_IDDIG_1P>; + input-enable; + bias-pull-up; + }; + + pins-vbus { + pinmux = <PINMUX_GPIO131__FUNC_USB_DRVVBUS_1P>; + output-low; + }; + }; + wifi_vreg_pins: wifi-vreg-pins { pins-wifi-pmu-en { pinmux = <PINMUX_GPIO65__FUNC_GPIO65>; @@ -709,6 +729,10 @@ status = "okay"; }; +&pciephy { + status = "okay"; +}; + &pmic { interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; }; @@ -776,6 +800,18 @@ }; }; +&u3phy0 { + status = "okay"; +}; + +&u3phy1 { + status = "okay"; +}; + +&u3phy2 { + status = "okay"; +}; + &uart0 { /* Exposed at 40 pin connector */ pinctrl-0 = <&uart0_pins>; @@ -791,6 +827,8 @@ }; &ssusb0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb3_port0_pins>; role-switch-default-mode = "host"; usb-role-switch; vusb33-supply = <&mt6359_vusb_ldo_reg>; @@ -804,6 +842,8 @@ }; &ssusb2 { + pinctrl-names = "default"; + pinctrl-0 = <&usb2_port0_pins>; vusb33-supply = <&mt6359_vusb_ldo_reg>; status = "okay"; }; |