diff options
author | Christian König <[email protected]> | 2018-10-04 19:31:27 +0200 |
---|---|---|
committer | Alex Deucher <[email protected]> | 2018-11-05 14:20:55 -0500 |
commit | 998d3fd4f8ce5714449237c2f93652e95ad476f4 (patch) | |
tree | 017c68978fefbe3f7f830ab56e1434b387daa884 | |
parent | 09f0b4ffd41e142f52f70640afd1b4b20288d627 (diff) |
drm/amdgpu: remove SRIOV specific handling from sdma_v4_0_gfx_resume
Just use the same code path for both SRIOV and bare metal.
Signed-off-by: Christian König <[email protected]>
Reviewed-by: Huang Rui <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 8 |
1 files changed, 1 insertions, 7 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index 49c8feb14d10..aa5bb9cfa738 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -725,11 +725,6 @@ static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i) /* before programing wptr to a less value, need set minor_ptr_update first */ WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); - if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ - WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2); - WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); - } - doorbell = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); doorbell_offset = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET)); @@ -745,8 +740,7 @@ static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i) adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, ring->doorbell_index); - if (amdgpu_sriov_vf(adev)) - sdma_v4_0_ring_set_wptr(ring); + sdma_v4_0_ring_set_wptr(ring); /* set minor_ptr_update to 0 after wptr programed */ WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); |