diff options
| author | Mikko Perttunen <[email protected]> | 2021-11-12 13:35:39 +0100 |
|---|---|---|
| committer | Thierry Reding <[email protected]> | 2021-12-16 16:51:00 +0100 |
| commit | 98094be152d34f8014ca67fbdc210e5261c4b09d (patch) | |
| tree | 6714061e0d6efccddf6dac55cf2622e96aae3167 | |
| parent | e537adde131bd4cf426e6d77f99060ca302e2f08 (diff) | |
arm64: tegra: Update Tegra234 BPMP channel addresses
On final Tegra234 systems, shared memory for communication with BPMP is
located at offset 0x70000 in SYSRAM.
Signed-off-by: Mikko Perttunen <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
| -rw-r--r-- | arch/arm64/boot/dts/nvidia/tegra234.dtsi | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 400c01acc19f..844cab44aee6 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -126,19 +126,19 @@ sram@40000000 { compatible = "nvidia,tegra234-sysram", "mmio-sram"; - reg = <0x0 0x40000000 0x0 0x50000>; + reg = <0x0 0x40000000 0x0 0x80000>; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x0 0x40000000 0x50000>; + ranges = <0x0 0x0 0x40000000 0x80000>; - cpu_bpmp_tx: sram@4e000 { - reg = <0x4e000 0x1000>; + cpu_bpmp_tx: sram@70000 { + reg = <0x70000 0x1000>; label = "cpu-bpmp-tx"; pool; }; - cpu_bpmp_rx: sram@4f000 { - reg = <0x4f000 0x1000>; + cpu_bpmp_rx: sram@71000 { + reg = <0x71000 0x1000>; label = "cpu-bpmp-rx"; pool; }; |