diff options
| author | Matt Roper <[email protected]> | 2022-04-27 21:19:24 -0700 |
|---|---|---|
| committer | Matt Roper <[email protected]> | 2022-04-29 14:30:21 -0700 |
| commit | 97e17a09063074a2534e8c2f4873588a9aaa48b3 (patch) | |
| tree | 66af30a6e82902f22d90ce04b38e7264fc80e53d | |
| parent | 991b4de3275728fd746ce15e00087fdbd51c29a1 (diff) | |
drm/i915/xehp: Add register for compute engine's MMIO-based TLB invalidation
Compute engines have a separate register that the driver should use to
perform MMIO-based TLB invalidation.
Note that the term "context" in this register's bspec description is
used to refer to the engine instance (in the same way "context" is used
on bspec 46167).
Bspec: 43930
Cc: Prathap Kumar Valsan <[email protected]>
Cc: Tvrtko Ursulin <[email protected]>
Signed-off-by: Matt Roper <[email protected]>
Acked-by: Tvrtko Ursulin <[email protected]>
Reviewed-by: Prathap Kumar Valsan <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_gt.c | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 92394f13b42f..53307ca0eed0 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -1175,6 +1175,7 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt) [VIDEO_DECODE_CLASS] = GEN12_VD_TLB_INV_CR, [VIDEO_ENHANCEMENT_CLASS] = GEN12_VE_TLB_INV_CR, [COPY_ENGINE_CLASS] = GEN12_BLT_TLB_INV_CR, + [COMPUTE_CLASS] = GEN12_COMPCTX_TLB_INV_CR, }; struct drm_i915_private *i915 = gt->i915; struct intel_uncore *uncore = gt->uncore; diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index a39718a40cc3..a0a49c16babd 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -1007,6 +1007,7 @@ #define GEN12_VD_TLB_INV_CR _MMIO(0xcedc) #define GEN12_VE_TLB_INV_CR _MMIO(0xcee0) #define GEN12_BLT_TLB_INV_CR _MMIO(0xcee4) +#define GEN12_COMPCTX_TLB_INV_CR _MMIO(0xcf04) #define GEN12_MERT_MOD_CTRL _MMIO(0xcf28) #define RENDER_MOD_CTRL _MMIO(0xcf2c) |