diff options
| author | Konstantin Aladyshev <[email protected]> | 2023-01-11 14:52:27 +0300 |
|---|---|---|
| committer | Joel Stanley <[email protected]> | 2023-01-23 14:16:48 +1030 |
| commit | 9664e1ba47fd27e2f21132ba6798c34adcaea288 (patch) | |
| tree | a2973d0c871df6d8f036040627a5a408a2499cf7 | |
| parent | 59e099e877d41b3a3ba79e6be425b73965f1aee9 (diff) | |
ARM: dts: aspeed: ethanolx: Enable CTS/RTS pins on UART1
BMC UART1 is connected to the P0 CPU UART1. As the connection has
CTS and RTS signals, enable these functions on the BMC side.
Signed-off-by: Konstantin Aladyshev <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Joel Stanley <[email protected]>
| -rw-r--r-- | arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts index e1f97721ada5..90feac5ec628 100644 --- a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts +++ b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts @@ -80,7 +80,9 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default>; + &pinctrl_rxd1_default + &pinctrl_nrts1_default + &pinctrl_ncts1_default>; }; &uart5 { |