diff options
| author | Tvrtko Ursulin <[email protected]> | 2019-04-18 11:06:34 +0100 |
|---|---|---|
| committer | Joonas Lahtinen <[email protected]> | 2019-04-30 10:16:18 +0300 |
| commit | 9628e15ca9d5f7595ba886173e98a139d0a56cd1 (patch) | |
| tree | 10198b36a3e5dd91f2c828f8784ceb95b6ca0d3e | |
| parent | 879a4e70f96a26a9368a3caed2f552aa67105852 (diff) | |
drm/i915/icl: Whitelist GEN9_SLICE_COMMON_ECO_CHICKEN1
WaEnableStateCacheRedirectToCS context workaround configures the L3 cache
to benefit 3d workloads but media has different requirements.
Remove the workaround and whitelist the register to allow any userspace
configure the behaviour to their liking.
v2:
* Remove the workaround apart from adding the whitelist.
Signed-off-by: Tvrtko Ursulin <[email protected]>
Cc: Lionel Landwerlin <[email protected]>
Cc: [email protected]
Cc: [email protected]
Acked-by: Lionel Landwerlin <[email protected]>
Acked-by: Anuj Phogat <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Fixes: f63c7b4880aa ("drm/i915/icl: WaEnableStateCacheRedirectToCS")
Reviewed-by: Joonas Lahtinen <[email protected]>
[tursulin: Anuj reported no GPU hangs or performance regressions with old
Mesa on patched kernel.]
(cherry picked from commit 0fc2273b9ab7f07cdef448e99525e481535e1ab0)
Signed-off-by: Joonas Lahtinen <[email protected]>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_workarounds.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c index ccaf63679435..9682dd575152 100644 --- a/drivers/gpu/drm/i915/intel_workarounds.c +++ b/drivers/gpu/drm/i915/intel_workarounds.c @@ -541,10 +541,6 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine) WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, GEN11_TDL_CLOCK_GATING_FIX_DISABLE); - /* WaEnableStateCacheRedirectToCS:icl */ - WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN1, - GEN11_STATE_CACHE_REDIRECT_TO_CS); - /* Wa_2006665173:icl (pre-prod) */ if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0)) WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, @@ -1050,6 +1046,9 @@ static void icl_whitelist_build(struct i915_wa_list *w) /* WaAllowUMDToModifySamplerMode:icl */ whitelist_reg(w, GEN10_SAMPLER_MODE); + + /* WaEnableStateCacheRedirectToCS:icl */ + whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); } void intel_engine_init_whitelist(struct intel_engine_cs *engine) |