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| author | Arnd Bergmann <[email protected]> | 2022-11-21 12:29:25 +0100 |
|---|---|---|
| committer | Arnd Bergmann <[email protected]> | 2022-11-21 12:29:26 +0100 |
| commit | 92f3bfaced6ef26ae2fa43c7952c80a31ba3d87d (patch) | |
| tree | 62f85ab8a808b61859ed15c233d43539fe173414 | |
| parent | 54721ff7d696b02b994fa736cd6613758078017b (diff) | |
| parent | 8292493c22c8e28b6e67a01e0f5c6db1cf231eb1 (diff) | |
Merge tag 'renesas-riscv-soc-for-v6.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/soc
Renesas RISC-V SoC updates for v6.2
- Add Kconfig option for Renesas RISC-V SoCs.
* tag 'renesas-riscv-soc-for-v6.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Arnd Bergmann <[email protected]>
| -rw-r--r-- | arch/riscv/Kconfig.socs | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 69774bb362d6..75fb0390d6bd 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -7,6 +7,11 @@ config SOC_MICROCHIP_POLARFIRE help This enables support for Microchip PolarFire SoC platforms. +config ARCH_RENESAS + bool "Renesas RISC-V SoCs" + help + This enables support for the RISC-V based Renesas SoCs. + config SOC_SIFIVE bool "SiFive SoCs" select SERIAL_SIFIVE if TTY |