diff options
| author | Steve Capper <[email protected]> | 2014-07-02 11:46:23 +0100 |
|---|---|---|
| committer | Catalin Marinas <[email protected]> | 2014-07-04 14:26:01 +0100 |
| commit | 923b8f5044da753e4985ab15c1374ced2cdf616c (patch) | |
| tree | 88431052c2658f46641708089975417bd981e86d | |
| parent | f3b766a26dd490026b9eb91a9136ade9f49fc674 (diff) | |
arm64: mm: Make icache synchronisation logic huge page aware
The __sync_icache_dcache routine will only flush the dcache for the
first page of a compound page, potentially leading to stale icache
data residing further on in a hugetlb page.
This patch addresses this issue by taking into consideration the
order of the page when flushing the dcache.
Reported-by: Mark Brown <[email protected]>
Tested-by: Mark Brown <[email protected]>
Signed-off-by: Steve Capper <[email protected]>
Acked-by: Will Deacon <[email protected]>
Signed-off-by: Catalin Marinas <[email protected]>
Cc: <[email protected]> # v3.11+
| -rw-r--r-- | arch/arm64/mm/flush.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm64/mm/flush.c b/arch/arm64/mm/flush.c index e4193e3adc7f..0d64089d28b5 100644 --- a/arch/arm64/mm/flush.c +++ b/arch/arm64/mm/flush.c @@ -79,7 +79,8 @@ void __sync_icache_dcache(pte_t pte, unsigned long addr) return; if (!test_and_set_bit(PG_dcache_clean, &page->flags)) { - __flush_dcache_area(page_address(page), PAGE_SIZE); + __flush_dcache_area(page_address(page), + PAGE_SIZE << compound_order(page)); __flush_icache_all(); } else if (icache_is_aivivt()) { __flush_icache_all(); |