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authorLucas Stach <[email protected]>2024-06-19 20:21:57 +0200
committerRobert Foss <[email protected]>2024-06-27 11:52:14 +0200
commit917c8d192ba6ada16b4cf11c786f3dbfe70de0d9 (patch)
tree6c498f8317818dae800d37837a2052425ec92061
parent90986e356c7a81d32550475f7de5bdc4cd878c2f (diff)
drm/bridge: analogix_dp: don't wait for PLL lock too early
The PLL will be reconfigured later, which may cause it to go out of lock anyway, so there is no point in waiting for the PLL to lock here. Instead we can continue execution of the link setup, which will properly set the PLL parameters and will wait for the PLL to lock at the appropriate times. Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Robert Foss <[email protected]> Tested-by: Heiko Stuebner <[email protected]> Signed-off-by: Robert Foss <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
-rw-r--r--drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c14
1 files changed, 1 insertions, 13 deletions
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index d267cf05cbca..e9c643a8b6fc 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -356,7 +356,6 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
int analogix_dp_init_analog_func(struct analogix_dp_device *dp)
{
u32 reg;
- int timeout_loop = 0;
analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
@@ -368,18 +367,7 @@ int analogix_dp_init_analog_func(struct analogix_dp_device *dp)
writel(reg, dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
/* Power up PLL */
- if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
- analogix_dp_set_pll_power_down(dp, 0);
-
- while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
- timeout_loop++;
- if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
- dev_err(dp->dev, "failed to get pll lock status\n");
- return -ETIMEDOUT;
- }
- usleep_range(10, 20);
- }
- }
+ analogix_dp_set_pll_power_down(dp, 0);
/* Enable Serdes FIFO function and Link symbol clock domain module */
reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);