diff options
author | Krzysztof Kozlowski <[email protected]> | 2024-04-02 22:07:41 +0200 |
---|---|---|
committer | Krzysztof Kozlowski <[email protected]> | 2024-04-24 09:23:55 +0200 |
commit | 915f104e558e409048a0c5137da91c4958a694b5 (patch) | |
tree | 12c3d4eb6c20a092fb4860b6408bf6f7d3603737 | |
parent | 71ef9c6212ef6b545f53b72328892251c72aa53d (diff) |
arm64: dts: amazon: alpine-v2: move non-MMIO node out of soc
Non-MMIO devices should not be within simple-bus, as reported by dtc W=1
warning:
alpine-v2.dtsi:100.9-106.5: Warning (simple_bus_reg): /soc/timer: missing or empty reg/ranges property
alpine-v2.dtsi:108.7-114.5: Warning (simple_bus_reg): /soc/pmu: missing or empty reg/ranges property
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
-rw-r--r-- | arch/arm64/boot/dts/amazon/alpine-v2.dtsi | 33 |
1 files changed, 17 insertions, 16 deletions
diff --git a/arch/arm64/boot/dts/amazon/alpine-v2.dtsi b/arch/arm64/boot/dts/amazon/alpine-v2.dtsi index 32b6ac8a5352..5b6b58dd44cb 100644 --- a/arch/arm64/boot/dts/amazon/alpine-v2.dtsi +++ b/arch/arm64/boot/dts/amazon/alpine-v2.dtsi @@ -39,6 +39,7 @@ / { model = "Annapurna Labs Alpine v2"; compatible = "al,alpine-v2"; + interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; @@ -89,6 +90,22 @@ clock-frequency = <1000000>; }; + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -97,22 +114,6 @@ interrupt-parent = <&gic>; ranges; - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; - }; - gic: interrupt-controller@f0200000 { compatible = "arm,gic-v3"; reg = <0x0 0xf0200000 0x0 0x10000>, /* GIC Dist */ |