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authorKan Liang <[email protected]>2020-10-19 08:35:27 -0700
committerPeter Zijlstra <[email protected]>2020-10-29 11:00:40 +0100
commit907a196fbc70a48338ee8512da32f70fd33c97eb (patch)
treea9216e2d879c328ff9768c49ea40ce72b36bd000
parentcbea56395cba13173fffb9251cb23f146b51c792 (diff)
perf/x86/msr: Add Rocket Lake CPU support
Like Ice Lake and Tiger Lake, PPERF and SMI_COUNT MSRs are also supported by Rocket Lake. Signed-off-by: Kan Liang <[email protected]> Signed-off-by: Peter Zijlstra (Intel) <[email protected]> Link: https://lkml.kernel.org/r/[email protected]
-rw-r--r--arch/x86/events/msr.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
index 4be8f9cabd07..680404c58cb1 100644
--- a/arch/x86/events/msr.c
+++ b/arch/x86/events/msr.c
@@ -99,6 +99,7 @@ static bool test_intel(int idx, void *data)
case INTEL_FAM6_ICELAKE_D:
case INTEL_FAM6_TIGERLAKE_L:
case INTEL_FAM6_TIGERLAKE:
+ case INTEL_FAM6_ROCKETLAKE:
if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)
return true;
break;