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authorKonrad Dybcio <[email protected]>2023-08-11 22:48:39 +0200
committerBjorn Andersson <[email protected]>2023-08-15 09:35:33 -0700
commit902824035fa5f2d2e9d20937cec331cbe52a1ab4 (patch)
treefc4e7d4e5357d1ee9a126c99838b91db0f0cdb6a
parent71f080633d1ee1233759484d790e86847d2434a5 (diff)
arm64: dts: qcom: sm6350: Hook up PDC as wakeup-parent of TLMM
Some TLMM pins are wakeup-capable. Describe the relationship between these two peripherals to enable this functionality. Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
-rw-r--r--arch/arm64/boot/dts/qcom/sm6350.dtsi1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 8f66306d1de3..8fd6f4d03490 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -2261,6 +2261,7 @@
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 157>;
+ wakeup-parent = <&pdc>;
cci0_default: cci0-default-state {
pins = "gpio39", "gpio40";