diff options
| author | Soren Brinkmann <[email protected]> | 2014-04-04 17:23:45 -0700 |
|---|---|---|
| committer | Michal Simek <[email protected]> | 2014-07-18 11:54:24 +0200 |
| commit | 8fe9346b945d76ddb3f08c00e34d701174c62fa0 (patch) | |
| tree | 090cd1371d5407257685f24455b9c11936091f6d | |
| parent | db34d2b32fa5edaf15f8aee6680be3722161d27a (diff) | |
ARM: zynq: DT: Migrate UART to Cadence binding
The Zynq UART is Cadence IP and the driver has been renamed accordingly.
Migrate the DT to use the new binding for the UART driver.
Signed-off-by: Soren Brinkmann <[email protected]>
Acked-by: Peter Crosthwaite <[email protected]>
Acked-by: Rob Herring <[email protected]>
Tested-by: Michal Simek <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
| -rw-r--r-- | arch/arm/boot/dts/zynq-7000.dtsi | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index 760bbc463c5b..029cbac30454 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -105,19 +105,19 @@ }; uart0: serial@e0000000 { - compatible = "xlnx,xuartps"; + compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 23>, <&clkc 40>; - clock-names = "ref_clk", "aper_clk"; + clock-names = "uart_clk", "pclk"; reg = <0xE0000000 0x1000>; interrupts = <0 27 4>; }; uart1: serial@e0001000 { - compatible = "xlnx,xuartps"; + compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 24>, <&clkc 41>; - clock-names = "ref_clk", "aper_clk"; + clock-names = "uart_clk", "pclk"; reg = <0xE0001000 0x1000>; interrupts = <0 50 4>; }; |