diff options
| author | Andy Shevchenko <[email protected]> | 2016-09-08 13:32:31 +0300 |
|---|---|---|
| committer | Ingo Molnar <[email protected]> | 2016-09-08 14:07:53 +0200 |
| commit | 8e522e1d321b12829960c9b26668c92f14c68d7f (patch) | |
| tree | 8774a3d995d9eba39c40e7ab299c85a1a8908e46 | |
| parent | f5fbf848303c8704d0e1a1e7cabd08fd0a49552f (diff) | |
x86/platform/intel-mid: Add Intel Penwell to ID table
Commit:
ca22312dc840 ("x86/platform/intel-mid: Extend PWRMU to support Penwell")
... enabled the PWRMU driver on platforms based on Intel Penwell, but
unfortunately this is not enough.
Add Intel Penwell ID to pci-mid.c driver as well. To avoid confusion in the
future add a comment to both drivers.
Signed-off-by: Andy Shevchenko <[email protected]>
Cc: Linus Torvalds <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Fixes: ca22312dc840 ("x86/platform/intel-mid: Extend PWRMU to support Penwell")
Link: http://lkml.kernel.org/r/[email protected]
Signed-off-by: Ingo Molnar <[email protected]>
| -rw-r--r-- | arch/x86/platform/intel-mid/pwr.c | 1 | ||||
| -rw-r--r-- | drivers/pci/pci-mid.c | 5 |
2 files changed, 6 insertions, 0 deletions
diff --git a/arch/x86/platform/intel-mid/pwr.c b/arch/x86/platform/intel-mid/pwr.c index 2dfe998a5afd..146ed54e92e5 100644 --- a/arch/x86/platform/intel-mid/pwr.c +++ b/arch/x86/platform/intel-mid/pwr.c @@ -427,6 +427,7 @@ static const struct mid_pwr_device_info mid_info = { .set_initial_state = mid_set_initial_state, }; +/* This table should be in sync with the one in drivers/pci/pci-mid.c */ static const struct pci_device_id mid_pwr_pci_ids[] = { { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PENWELL), (kernel_ulong_t)&mid_info }, { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_TANGIER), (kernel_ulong_t)&mid_info }, diff --git a/drivers/pci/pci-mid.c b/drivers/pci/pci-mid.c index b7ea64f63149..55f453de562e 100644 --- a/drivers/pci/pci-mid.c +++ b/drivers/pci/pci-mid.c @@ -60,7 +60,12 @@ static struct pci_platform_pm_ops mid_pci_platform_pm = { #define ICPU(model) { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, } +/* + * This table should be in sync with the one in + * arch/x86/platform/intel-mid/pwr.c. + */ static const struct x86_cpu_id lpss_cpu_ids[] = { + ICPU(INTEL_FAM6_ATOM_PENWELL), ICPU(INTEL_FAM6_ATOM_MERRIFIELD), {} }; |