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authorYongqiang Sun <[email protected]>2017-11-17 10:44:15 -0500
committerAlex Deucher <[email protected]>2017-12-14 10:53:32 -0500
commit8e504bccc11663c3b334ef1a7698e18a967de920 (patch)
tree860bc596e978d917e5e0369f672d0a8f00f612c8
parent9168a586e865083646e737a19ab38db8f1dcff3e (diff)
drm/amd/display: Disable plane right after disconnected
HDR display playing video underflow is observed when switching to full screen due to program a lower watermark right after unlock otg. Instead of disable plane in next flip coming, if there is a plane disconnected, after otg unlock wait for mpcc idle and disable the plane, then program watermark. So there is enough warter mark to make sure current frame data pass through. Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 1ebe980bfb6d..d542e4db5495 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2297,7 +2297,7 @@ static void dcn10_apply_ctx_for_surface(
pipe_ctx->plane_state->update_flags.bits.full_update)
program_water_mark = true;
- if (removed_pipe[i] && num_planes == 0)
+ if (removed_pipe[i])
dcn10_disable_plane(dc, old_pipe_ctx);
}
@@ -2306,6 +2306,7 @@ static void dcn10_apply_ctx_for_surface(
/* pstate stuck check after watermark update */
dcn10_verify_allow_pstate_change_high(dc);
}
+
/* watermark is for all pipes */
hubbub1_program_watermarks(dc->res_pool->hubbub,
&context->bw.dcn.watermarks, ref_clk_mhz);