diff options
| author | Pierre Gondois <[email protected]> | 2023-10-20 14:50:22 -0500 |
|---|---|---|
| committer | Arnd Bergmann <[email protected]> | 2023-10-23 21:10:34 +0200 |
| commit | 8d4f9145f52e9d1c5e6e86402ef8ca24cadb38f9 (patch) | |
| tree | a30995650868bb8c52938d7ab84e6a860f532070 | |
| parent | 23b336e9825d998dfc7035a8826cb9b26fb75b4d (diff) | |
arm64: dts: Update cache properties for socionext
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <[email protected]>
Reviewed-by: Kunihiko Hayashi <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Rob Herring <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Arnd Bergmann <[email protected]>
| -rw-r--r-- | arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 1 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 2 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 1 |
3 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi index 7bb36b071475..54e58d945fd7 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi @@ -52,6 +52,7 @@ l2: l2-cache { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index 4e2171630272..18390cba2eda 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -86,10 +86,12 @@ a72_l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; a53_l2: l2-cache1 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi index 38ccfb46ea42..56e037900818 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi @@ -83,6 +83,7 @@ l2: l2-cache { compatible = "cache"; + cache-level = <2>; }; }; |