diff options
| author | Odelu Kukatla <[email protected]> | 2021-10-21 16:10:57 +0530 |
|---|---|---|
| committer | Bjorn Andersson <[email protected]> | 2022-02-23 13:10:32 -0600 |
| commit | 8b93fbd95ed46bb0d57e63c65cef155a09a75bb9 (patch) | |
| tree | 0ef9e018f3027290d3a60c35f674847480a8db87 | |
| parent | 1dc3e50eb68031bc8fc56829c7ac46c89dfbe237 (diff) | |
arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider
Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280
SoCs.
Signed-off-by: Odelu Kukatla <[email protected]>
Acked-by: Georgi Djakov <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 3572399282d8..c6d26ea805d8 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -4296,6 +4296,14 @@ }; }; + epss_l3: interconnect@18590000 { + compatible = "qcom,sc7280-epss-l3"; + reg = <0 0x18590000 0 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + #interconnect-cells = <1>; + }; + cpufreq_hw: cpufreq@18591000 { compatible = "qcom,cpufreq-epss"; reg = <0 0x18591000 0 0x1000>, |