diff options
| author | Vinod Govindapillai <[email protected]> | 2023-11-11 13:43:20 +0200 |
|---|---|---|
| committer | Mika Kahola <[email protected]> | 2023-11-15 09:40:18 +0200 |
| commit | 8a4353d077788b4efb11beb8c4e3869ea7aeaff7 (patch) | |
| tree | ed9adb02cd30dcc4ad49af42d7589583a2a069ab | |
| parent | dd99d5b1ab93e7b731dda3d39cc7caf4639f8652 (diff) | |
drm/i915/xe2lpd: implement WA for underruns while enabling FBC
FIFO underruns are observed when FBC is enabled on plane 2 or
plane 3. Recommended WA is to update the FBC enabling sequence.
The plane binding register bits need to be updated separately
before programming the FBC enable bit.
Bspec: 74151
Reviewed-by: Mika Kahola <[email protected]> #v3
Signed-off-by: Vinod Govindapillai <[email protected]>
Reviewed-by: Mika Kahola <[email protected]>
Signed-off-by: Mika Kahola <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_fbc.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index bde12fe62275..b73cf1c5ba33 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -608,6 +608,7 @@ static u32 ivb_dpfc_ctl(struct intel_fbc *fbc) static void ivb_fbc_activate(struct intel_fbc *fbc) { struct drm_i915_private *i915 = fbc->i915; + u32 dpfc_ctl; if (DISPLAY_VER(i915) >= 10) glk_fbc_program_cfb_stride(fbc); @@ -617,8 +618,13 @@ static void ivb_fbc_activate(struct intel_fbc *fbc) if (intel_gt_support_legacy_fencing(to_gt(i915))) snb_fbc_program_fence(fbc); + /* wa_14019417088 Alternative WA*/ + dpfc_ctl = ivb_dpfc_ctl(fbc); + if (DISPLAY_VER(i915) >= 20) + intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl); + intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), - DPFC_CTL_EN | ivb_dpfc_ctl(fbc)); + DPFC_CTL_EN | dpfc_ctl); } static bool ivb_fbc_is_compressing(struct intel_fbc *fbc) |