diff options
author | Yangtao Li <[email protected]> | 2020-04-20 15:00:13 +0200 |
---|---|---|
committer | Maxime Ripard <[email protected]> | 2020-04-20 15:23:01 +0200 |
commit | 8a3a9535189d908f7e325238c9f09069d4fe9b8f (patch) | |
tree | b4c059a12b67d5bf645e5ec55021966191197f16 | |
parent | 3d478d211b8e40deb609594f0676be205e8d89c1 (diff) |
arm64: dts: allwinner: h6: Add clock to CPU cores
The ARM CPU cores are fed by the CPU clock from the CCU. Add a
reference to the clock for each CPU core, along with the clock
transition latency.
Signed-off-by: Yangtao Li <[email protected]>
Signed-off-by: Clément Péron <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
-rw-r--r-- | arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index a5ee68388bd3..370e77b86fe1 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -25,6 +25,8 @@ device_type = "cpu"; reg = <0>; enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; + clock-latency-ns = <244144>; /* 8 32k periods */ }; cpu1: cpu@1 { @@ -32,6 +34,8 @@ device_type = "cpu"; reg = <1>; enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; + clock-latency-ns = <244144>; /* 8 32k periods */ }; cpu2: cpu@2 { @@ -39,6 +43,8 @@ device_type = "cpu"; reg = <2>; enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; + clock-latency-ns = <244144>; /* 8 32k periods */ }; cpu3: cpu@3 { @@ -46,6 +52,8 @@ device_type = "cpu"; reg = <3>; enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; + clock-latency-ns = <244144>; /* 8 32k periods */ }; }; |