diff options
| author | Sean Anderson <[email protected]> | 2021-06-07 15:05:46 -0400 |
|---|---|---|
| committer | Rob Herring <[email protected]> | 2021-06-21 13:56:01 -0600 |
| commit | 89f8a707d00890d302f6d4320d4ecdba12c26bdf (patch) | |
| tree | 2adbbc650cb86624b3b90631eeab9292028866bc | |
| parent | cdbbe6ce26f6e991014596e50d6be280fbc302be (diff) | |
dt-bindings: clk: vc5: Fix example
The example properties do not match the binding. Fix them, and prohibit
undocumented properties in clock nodes to prevent this from happening in
the future.
Fixes: 45c940184b50 ("dt-bindings: clk: versaclock5: convert to yaml")
Signed-off-by: Sean Anderson <[email protected]>
Reviewed-by: Luca Ceresoli <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Rob Herring <[email protected]>
| -rw-r--r-- | Documentation/devicetree/bindings/clock/idt,versaclock5.yaml | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml b/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml index c268debe5b8d..241e1f2554e7 100644 --- a/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml +++ b/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml @@ -86,6 +86,7 @@ patternProperties: description: The Slew rate control for CMOS single-ended. $ref: /schemas/types.yaml#/definitions/uint32 enum: [ 80, 85, 90, 100 ] + additionalProperties: false required: - compatible @@ -141,13 +142,13 @@ examples: clock-names = "xin"; OUT1 { - idt,drive-mode = <VC5_CMOSD>; - idt,voltage-microvolts = <1800000>; + idt,mode = <VC5_CMOSD>; + idt,voltage-microvolt = <1800000>; idt,slew-percent = <80>; }; OUT4 { - idt,drive-mode = <VC5_LVDS>; + idt,mode = <VC5_LVDS>; }; }; }; |