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authorConor Dooley <[email protected]>2023-02-28 19:26:55 -0500
committerStephen Boyd <[email protected]>2023-03-06 14:41:20 -0800
commit89dc65a7cc8a119c395c0931b12d7a514f9d2bcc (patch)
tree3afa1bfee774f1d1173abb0c469909d3854b1049
parent26243872fe26ec0df7d81766253d00213990e382 (diff)
clk: k210: remove an implicit 64-bit division
The K210 clock driver depends on SOC_CANAAN, which is only selectable when !MMU on RISC-V. !MMU is not possible on 32-bit yet, but patches have been sent for its enabling. The kernel test robot reported this implicit 64-bit division there. Replace the implicit division with an explicit one. Reported-by: kernel test robot <[email protected]> Link: https://lore.kernel.org/linux-riscv/[email protected]/ Signed-off-by: Conor Dooley <[email protected]> Signed-off-by: Jesse Taube <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Damien Le Moal <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
-rw-r--r--drivers/clk/clk-k210.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/clk-k210.c b/drivers/clk/clk-k210.c
index 67a7cb3503c3..4eed667eddaf 100644
--- a/drivers/clk/clk-k210.c
+++ b/drivers/clk/clk-k210.c
@@ -495,7 +495,7 @@ static unsigned long k210_pll_get_rate(struct clk_hw *hw,
f = FIELD_GET(K210_PLL_CLKF, reg) + 1;
od = FIELD_GET(K210_PLL_CLKOD, reg) + 1;
- return (u64)parent_rate * f / (r * od);
+ return div_u64((u64)parent_rate * f, r * od);
}
static const struct clk_ops k210_pll_ops = {