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authorJani Nikula <jani.nikula@intel.com>2024-05-23 15:59:39 +0300
committerJani Nikula <jani.nikula@intel.com>2024-05-24 10:41:05 +0300
commit89b85751b4fda1918cf314318d61a184218d3df3 (patch)
tree58c58be2b760ea0c821fc6eb088414a39981112c
parent495d6f77dfa79b26bfa95eca3215179659c2cf8e (diff)
drm/i915: pass dev_priv explicitly to DSPSURFLIVE
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPSURFLIVE register macro. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/bc252dee67718f729883da7d542c6435384683ae.1716469091.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
-rw-r--r--drivers/gpu/drm/i915/display/i9xx_plane_regs.h2
-rw-r--r--drivers/gpu/drm/i915/gvt/handlers.c4
-rw-r--r--drivers/gpu/drm/i915/intel_gvt_mmio_table.c6
3 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
index 0930a76ccf3c..22a550c8b41a 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
@@ -81,7 +81,7 @@
#define DSPOFFSET(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET)
#define _DSPASURFLIVE 0x701AC /* g4x+ */
-#define DSPSURFLIVE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE)
+#define DSPSURFLIVE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE)
#define _DSPAGAMC 0x701E0 /* pre-g4x */
#define DSPGAMC(plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index abcb8f0825e0..840fea160aa6 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1018,7 +1018,7 @@ static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
int event = SKL_FLIP_EVENT(pipe, PLANE_PRIMARY);
write_vreg(vgpu, offset, p_data, bytes);
- vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
+ vgpu_vreg_t(vgpu, DSPSURFLIVE(dev_priv, pipe)) = vgpu_vreg(vgpu, offset);
vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
@@ -1061,7 +1061,7 @@ static int reg50080_mmio_write(struct intel_vgpu *vgpu,
write_vreg(vgpu, offset, p_data, bytes);
if (plane == PLANE_PRIMARY) {
- vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
+ vgpu_vreg_t(vgpu, DSPSURFLIVE(dev_priv, pipe)) = vgpu_vreg(vgpu, offset);
vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
} else {
vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 50dfe1f81b99..b4d5592b18df 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -172,7 +172,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(DSPSIZE(dev_priv, PIPE_A));
MMIO_D(DSPSURF(dev_priv, PIPE_A));
MMIO_D(DSPOFFSET(dev_priv, PIPE_A));
- MMIO_D(DSPSURFLIVE(PIPE_A));
+ MMIO_D(DSPSURFLIVE(dev_priv, PIPE_A));
MMIO_D(REG_50080(PIPE_A, PLANE_PRIMARY));
MMIO_D(DSPCNTR(dev_priv, PIPE_B));
MMIO_D(DSPADDR(dev_priv, PIPE_B));
@@ -181,7 +181,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(DSPSIZE(dev_priv, PIPE_B));
MMIO_D(DSPSURF(dev_priv, PIPE_B));
MMIO_D(DSPOFFSET(dev_priv, PIPE_B));
- MMIO_D(DSPSURFLIVE(PIPE_B));
+ MMIO_D(DSPSURFLIVE(dev_priv, PIPE_B));
MMIO_D(REG_50080(PIPE_B, PLANE_PRIMARY));
MMIO_D(DSPCNTR(dev_priv, PIPE_C));
MMIO_D(DSPADDR(dev_priv, PIPE_C));
@@ -190,7 +190,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(DSPSIZE(dev_priv, PIPE_C));
MMIO_D(DSPSURF(dev_priv, PIPE_C));
MMIO_D(DSPOFFSET(dev_priv, PIPE_C));
- MMIO_D(DSPSURFLIVE(PIPE_C));
+ MMIO_D(DSPSURFLIVE(dev_priv, PIPE_C));
MMIO_D(REG_50080(PIPE_C, PLANE_PRIMARY));
MMIO_D(SPRCTL(PIPE_A));
MMIO_D(SPRLINOFF(PIPE_A));