diff options
| author | Chao Hao <[email protected]> | 2020-07-03 12:41:26 +0800 |
|---|---|---|
| committer | Joerg Roedel <[email protected]> | 2020-07-10 16:13:11 +0200 |
| commit | 864444130eed304835b09c86a5bf2ff05bc2f4a2 (patch) | |
| tree | 7e77da511f06b82979e428ef541e907e63274c05 | |
| parent | 829316b3bc897a3275a0354505fde3ccd0053936 (diff) | |
iommu/mediatek: Modify MMU_CTRL register setting
The MMU_CTRL register of MT8173 is different from other SoCs.
The in_order_wr_en is bit[9] which is zero by default.
Other SoCs have the vitcim_tlb_en feature mapped to bit[12].
This bit is set to one by default. We need to preserve the bit
when setting F_MMU_TF_PROT_TO_PROGRAM_ADDR as otherwise the
bit will be cleared and IOMMU performance will drop.
Signed-off-by: Chao Hao <[email protected]>
Reviewed-by: Matthias Brugger <[email protected]>
Cc: Matthias Brugger <[email protected]>
Cc: Yong Wu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Joerg Roedel <[email protected]>
| -rw-r--r-- | drivers/iommu/mtk_iommu.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index e71003037ffa..a816030d00f1 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -555,11 +555,13 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) return ret; } - if (data->plat_data->m4u_plat == M4U_MT8173) + if (data->plat_data->m4u_plat == M4U_MT8173) { regval = F_MMU_PREFETCH_RT_REPLACE_MOD | F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173; - else - regval = F_MMU_TF_PROT_TO_PROGRAM_ADDR; + } else { + regval = readl_relaxed(data->base + REG_MMU_CTRL_REG); + regval |= F_MMU_TF_PROT_TO_PROGRAM_ADDR; + } writel_relaxed(regval, data->base + REG_MMU_CTRL_REG); regval = F_L2_MULIT_HIT_EN | |