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authorRajneesh Bhardwaj <[email protected]>2018-02-02 19:13:35 +0530
committerAndy Shevchenko <[email protected]>2018-02-04 15:55:52 +0200
commit850eb9fba3711e98bafebde26675d9c082c0ff48 (patch)
tree12454023f3a8b248586e531063d3111608fe681d
parent745698c37c08f48fb5ad3c0cb7ee955bd5701d4a (diff)
x86/cpu: Add Cannonlake to Intel family
Add CPUID of Cannonlake (CNL) processors to Intel family list. Cc: Dave Hansen <[email protected]> Cc: Thomas Gleixner <[email protected]> cc: Ingo Molnar <[email protected]> Cc: "H. Peter Anvin" <[email protected]> Cc: [email protected] Reviewed-by: Thomas Gleixner <[email protected]> Suggested-by: Tony Luck <[email protected]> Signed-off-by: Megha Dey <[email protected]> Signed-off-by: Rajneesh Bhardwaj <[email protected]> Signed-off-by: Andy Shevchenko <[email protected]>
-rw-r--r--arch/x86/include/asm/intel-family.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h
index 35a6bc4da8ad..cf090e584202 100644
--- a/arch/x86/include/asm/intel-family.h
+++ b/arch/x86/include/asm/intel-family.h
@@ -10,6 +10,10 @@
*
* Things ending in "2" are usually because we have no better
* name for them. There's no processor called "SILVERMONT2".
+ *
+ * While adding a new CPUID for a new microarchitecture, add a new
+ * group to keep logically sorted out in chronological order. Within
+ * that group keep the CPUID for the variants sorted by model number.
*/
#define INTEL_FAM6_CORE_YONAH 0x0E
@@ -49,6 +53,8 @@
#define INTEL_FAM6_KABYLAKE_MOBILE 0x8E
#define INTEL_FAM6_KABYLAKE_DESKTOP 0x9E
+#define INTEL_FAM6_CANNONLAKE_MOBILE 0x66
+
/* "Small Core" Processors (Atom) */
#define INTEL_FAM6_ATOM_PINEVIEW 0x1C