diff options
| author | Chris Park <[email protected]> | 2024-05-27 21:21:30 -0400 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2024-06-14 16:17:15 -0400 |
| commit | 8362061eed6761a36866876ba2dd00ec638a13b4 (patch) | |
| tree | 303965f6e9c65f5df230f0ae3f1d4a90318bdcb4 | |
| parent | ed79ab5a07c1cb4bb05422ac6e794e40c4c1484c (diff) | |
drm/amd/display: Prevent overflow on DTO calculation
[Why]
uint32_t is implicitly converted to uint64_t while multiplication
still happens on uint32_t side. This creates digit overflow
for large pixel clock which is meant to be retained in uint64_t.
[How]
Calculate multiplication of units in uint64_t domain instead of
uint32_t in DTO parameter clock caculation.
Reviewed-by: Alvin Lee <[email protected]>
Acked-by: Zaeem Mohamed <[email protected]>
Signed-off-by: Chris Park <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index 63deb5b60548..042a4187fff4 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -1088,11 +1088,15 @@ static bool dcn401_program_pix_clk( dto_params.clk_src = DPREFCLK; if (e) { - dto_params.pixclk_hz = e->target_pixel_rate_khz * e->mult_factor; - dto_params.refclk_hz = dtbclk_p_src_clk_khz * e->div_factor; + dto_params.pixclk_hz = e->target_pixel_rate_khz; + dto_params.pixclk_hz *= e->mult_factor; + dto_params.refclk_hz = dtbclk_p_src_clk_khz; + dto_params.refclk_hz *= e->div_factor; } else { - dto_params.pixclk_hz = pix_clk_params->requested_pix_clk_100hz * 100; - dto_params.refclk_hz = dtbclk_p_src_clk_khz * 1000; + dto_params.pixclk_hz = pix_clk_params->requested_pix_clk_100hz; + dto_params.pixclk_hz *= 100; + dto_params.refclk_hz = dtbclk_p_src_clk_khz; + dto_params.refclk_hz *= 1000; } /* enable DP DTO */ |