diff options
| author | Jernej Skrabec <[email protected]> | 2019-10-01 22:06:56 +0200 |
|---|---|---|
| committer | Maxime Ripard <[email protected]> | 2019-10-02 08:05:40 +0200 |
| commit | 834f65e18c82d10b781bee2ad207b590574eeaf9 (patch) | |
| tree | 12db3e4144b111c2141765e2dbc24735694e70e0 | |
| parent | 3ee5f8ab5e718afdde9984a089137360bdfc66eb (diff) | |
clk: sunxi-ng: h6: Allow GPU to change parent rate
GPU PLL was designed with dynamic frequency switching in mind so driver
can adjust rate based on the GPU load.
Allow GPU clock to change parent rate (GPU PLL is the only possible
parent of GPU clock).
Signed-off-by: Jernej Skrabec <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
| -rw-r--r-- | drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c index ed6338d74474..f2497d0a4683 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c @@ -299,7 +299,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(gpu_clk, "gpu", gpu_parents, 0x670, 0, 3, /* M */ 24, 1, /* mux */ BIT(31), /* gate */ - 0); + CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2", 0x67c, BIT(0), 0); |