diff options
| author | Shaik Sajida Bhanu <[email protected]> | 2021-06-10 12:41:47 +0530 |
|---|---|---|
| committer | Bjorn Andersson <[email protected]> | 2021-06-14 11:29:46 -0500 |
| commit | 81cfa462e458405f58b23f45ddd9439c70bf5347 (patch) | |
| tree | 057ef9a5765c0aa96400d196fe38607fcf680ed4 | |
| parent | 297e6e38320f325eb6763e48847e7dd06fda694b (diff) | |
arm64: dts: qcom: sc7180: Add xo clock for eMMC and Sd card
The calculations for the DLL register values are based on the clock rate
of the reference clock. Provide the reference clock in the definition of
the two SDHCI controllers to not rely on the default values.
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Shaik Sajida Bhanu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[bjorn: Rewrote commit message]
Signed-off-by: Bjorn Andersson <[email protected]>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sc7180.dtsi | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 52115e0359bd..fb1d9ad8bf6c 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -701,8 +701,9 @@ interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>; - clock-names = "core", "iface"; + <&gcc GCC_SDCC1_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "core", "iface", "xo"; interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>; interconnect-names = "sdhc-ddr","cpu-sdhc"; @@ -2564,8 +2565,9 @@ interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>; - clock-names = "core", "iface"; + <&gcc GCC_SDCC2_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "core", "iface", "xo"; interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; |