diff options
| author | Eugen Hristev <[email protected]> | 2019-09-11 06:39:20 +0000 |
|---|---|---|
| committer | Stephen Boyd <[email protected]> | 2019-09-17 22:00:31 -0700 |
| commit | 81a6b601f9f49be4e5972c351ad27cb13265c225 (patch) | |
| tree | 44558897d1ce28c7fac4841f2d059dced7cdfee9 | |
| parent | 69a6bcde7fd3fe6f3268ce26f31d9d9378384c98 (diff) | |
clk: at91: allow 24 Mhz clock as input for PLL
The PLL input range needs to be able to allow 24 Mhz crystal as input
Update the range accordingly in plla characteristics struct
Signed-off-by: Eugen Hristev <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]
Acked-by: Nicolas Ferre <[email protected]>
Fixes: c561e41ce4d2 ("clk: at91: add sama5d2 PMC driver")
Signed-off-by: Stephen Boyd <[email protected]>
| -rw-r--r-- | drivers/clk/at91/sama5d2.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c index 6509d0934804..0de1108737db 100644 --- a/drivers/clk/at91/sama5d2.c +++ b/drivers/clk/at91/sama5d2.c @@ -21,7 +21,7 @@ static const struct clk_range plla_outputs[] = { }; static const struct clk_pll_characteristics plla_characteristics = { - .input = { .min = 12000000, .max = 12000000 }, + .input = { .min = 12000000, .max = 24000000 }, .num_output = ARRAY_SIZE(plla_outputs), .output = plla_outputs, .icpll = plla_icpll, |