diff options
| author | Alvin Lee <[email protected]> | 2023-04-28 17:29:02 -0400 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2023-06-09 09:35:11 -0400 |
| commit | 807a1c14276b6ba6dc7efb4784ac35bceea1413f (patch) | |
| tree | 39a6587cca87913119d901fe6b6b2024a4275f4b | |
| parent | a00e595207d001432a85758954c3a6f6a9896368 (diff) | |
drm/amd/display: Block SubVP on displays that have pixclk > 1800Mhz
[Description]
- Enabling SubVP on high refresh rate displays had a side effect
of also enabling on high bandwidth displays such as 8K60
- However, these are not validated and should be blocked for
the time being
- Block SubVP on displays that have pix rate > 1800Mhz (includes
8K60 displays)
Reviewed-by: Jun Lei <[email protected]>
Reviewed-by: Nevenko Stupar <[email protected]>
Cc: Mario Limonciello <[email protected]>
Cc: Alex Deucher <[email protected]>
Cc: [email protected]
Acked-by: Alex Hung <[email protected]>
Signed-off-by: Alvin Lee <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h index 04be01ae1ecf..42ccfd13a37c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h @@ -41,6 +41,7 @@ #define DCN3_2_DCFCLK_DS_INIT_KHZ 10000 // Choose 10Mhz for init DCFCLK DS freq #define DCN3_2_MIN_ACTIVE_SWITCH_MARGIN_FPO_US 100 // Only allow FPO + Vactive if active margin >= 100 #define SUBVP_HIGH_REFRESH_LIST_LEN 3 +#define DCN3_2_MAX_SUBVP_PIXEL_RATE_MHZ 1800 #define TO_DCN32_RES_POOL(pool)\ container_of(pool, struct dcn32_resource_pool, base) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c index cd28980b2b56..f7e45d935a29 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c @@ -703,6 +703,7 @@ static bool dcn32_assign_subvp_pipe(struct dc *dc, * - Not TMZ surface */ if (pipe->plane_state && !pipe->top_pipe && !dcn32_is_center_timing(pipe) && + !(pipe->stream->timing.pix_clk_100hz / 10000 > DCN3_2_MAX_SUBVP_PIXEL_RATE_MHZ) && (!dcn32_is_psr_capable(pipe) || (context->stream_count == 1 && dc->caps.dmub_caps.subvp_psr)) && pipe->stream->mall_stream_config.type == SUBVP_NONE && (refresh_rate < 120 || dcn32_allow_subvp_high_refresh_rate(dc, context, pipe)) && |