diff options
| author | Christian Marangi <[email protected]> | 2022-07-07 03:09:43 +0200 |
|---|---|---|
| committer | Bjorn Andersson <[email protected]> | 2022-07-16 21:44:38 -0500 |
| commit | 7f5aecdd4ffcc018f73171bc0e028cd4e3361acd (patch) | |
| tree | ddf727cdbcbbd3038b865637a5c29ae55c134e98 | |
| parent | 6c421a9c08286389bb331fe783e2625c9efcc187 (diff) | |
ARM: dts: qcom: ipq8064: add speedbin efuse nvmem node
Add speedbin efuse nvmem cell needed for the opp table for the CPU
freqs.
Signed-off-by: Christian Marangi <[email protected]>
Tested-by: Jonathan McDowell <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
| -rw-r--r-- | arch/arm/boot/dts/qcom-ipq8064.dtsi | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 69cf664851c6..71572028bc36 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -854,6 +854,9 @@ reg = <0x00700000 0x1000>; #address-cells = <1>; #size-cells = <1>; + speedbin_efuse: speedbin@c0 { + reg = <0xc0 0x4>; + }; tsens_calib: calib@400 { reg = <0x400 0xb>; }; |