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| author | Damien Le Moal <[email protected]> | 2021-02-10 14:02:17 +0900 |
|---|---|---|
| committer | Palmer Dabbelt <[email protected]> | 2021-02-22 17:51:07 -0800 |
| commit | 7ef71c719eb462edaa6078405654d2447c7a5488 (patch) | |
| tree | a8fb2206ac860afbd2e83bb65b6ccd1123ab2c91 | |
| parent | 11481d6b5783fe4b6a6ba2870e49da4b4ebb2259 (diff) | |
dt-bindings: update risc-v cpu properties
The Canaan Kendryte K210 SoC CPU cores are based on a rocket chip
version using a draft verion of the RISC-V ISA specifications. To avoid
any confusion with CPU cores using stable specifications, add the
compatible string "canaan,k210" for this SoC CPU cores.
Also add the "riscv,none" value to the mmu-type property to allow a DT
to indicate that the CPU being described does not have an MMU or that
it has an MMU that is not usable (which is the case for the K210 SoC).
Signed-off-by: Damien Le Moal <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Palmer Dabbelt <[email protected]>
| -rw-r--r-- | Documentation/devicetree/bindings/riscv/cpus.yaml | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index eb6843f69f7c..e534f6a7cfa1 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -39,6 +39,7 @@ properties: - sifive,u74 - sifive,u5 - sifive,u7 + - canaan,k210 - const: riscv - const: riscv # Simulator only description: @@ -56,6 +57,7 @@ properties: - riscv,sv32 - riscv,sv39 - riscv,sv48 + - riscv,none riscv,isa: description: |