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authorAngeloGioacchino Del Regno <[email protected]>2023-03-27 10:36:40 +0200
committerMatthias Brugger <[email protected]>2023-04-11 18:36:46 +0200
commit7eb1f2c61fb0edf4211ac379a6f2c1c250460f9e (patch)
treeb12a0fa5aded0fc3f5f5d9edda86a533c8bcdee7
parent80dd5ca523c5bbef082c31fad67825009bfb04d6 (diff)
arm64: dts: mediatek: mt6795: Add VDECSYS and VENCSYS clocks
In prepration for adding the IOMMUs and LARBs of this SoC, add the VDECSYS and VENCSYS clock controller nodes, providing clocks for the vcodec stateful decoder and stateful decoder hardware. Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matthias Brugger <[email protected]>
-rw-r--r--arch/arm64/boot/dts/mediatek/mt6795.dtsi12
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index d63efb32e6bb..090400d7fd61 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -624,5 +624,17 @@
clock-names = "source", "hclk";
status = "disabled";
};
+
+ vdecsys: clock-controller@16000000 {
+ compatible = "mediatek,mt6795-vdecsys";
+ reg = <0 0x16000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vencsys: clock-controller@18000000 {
+ compatible = "mediatek,mt6795-vencsys";
+ reg = <0 0x18000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
};
};