diff options
| author | Andrea Merello <[email protected]> | 2018-11-20 16:31:47 +0100 |
|---|---|---|
| committer | Vinod Koul <[email protected]> | 2019-01-07 09:53:11 +0530 |
| commit | 7df54dbeb055229f6689161aa90bf00bf4af077e (patch) | |
| tree | 6b2b4908d262c5aec1fdc2bb2ca25371adaf8161 | |
| parent | 5c094d4cac5ba78139f4d7169145b57af7f07981 (diff) | |
dt-bindings: dmaengine: xilinx_dma: add optional xlnx,sg-length-width property
The width of the "length register" cannot be autodetected, and it is now
specified with a DT property. Add documentation for it.
Cc: Rob Herring <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: [email protected]
Cc: Radhey Shyam Pandey <[email protected]>
Signed-off-by: Andrea Merello <[email protected]>
Reviewed-by: Radhey Shyam Pandey <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Vinod Koul <[email protected]>
| -rw-r--r-- | Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt index 174af2c45e77..2fce9fb4b270 100644 --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt @@ -41,6 +41,10 @@ Optional properties: - xlnx,include-sg: Tells configured for Scatter-mode in the hardware. Optional properties for AXI DMA: +- xlnx,sg-length-width: Should be set to the width in bits of the length + register as configured in h/w. Takes values {8...26}. If the property + is missing or invalid then the default value 23 is used. This is the + maximum value that is supported by all IP versions. - xlnx,mcdma: Tells whether configured for multi-channel mode in the hardware. Optional properties for VDMA: - xlnx,flush-fsync: Tells which channel to Flush on Frame sync. |