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authorUros Bizjak <[email protected]>2023-11-09 21:09:56 +0100
committerBorislav Petkov (AMD) <[email protected]>2023-12-13 13:35:38 +0100
commit7d28365a06af74cee015a448d32ab6e98cd05cfb (patch)
tree70fb5cad9cec88a0c061ecaa66f30fc2e9b0cec9
parent7a0a6d55ed93fe064039c4e014d5cf3a97391bbb (diff)
x86/head_64: Use TESTB instead of TESTL in secondary_startup_64_no_verify()
There is no need to use TESTL when checking the least-significant bit with a TEST instruction. Use TESTB, which is three bytes shorter: f6 05 00 00 00 00 01 testb $0x1,0x0(%rip) vs: f7 05 00 00 00 00 01 testl $0x1,0x0(%rip) 00 00 00 for the same effect. No functional changes intended. Signed-off-by: Uros Bizjak <[email protected]> Signed-off-by: Borislav Petkov (AMD) <[email protected]> Link: https://lore.kernel.org/r/[email protected]
-rw-r--r--arch/x86/kernel/head_64.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S
index 086a2c3aaaa0..1f79d809305d 100644
--- a/arch/x86/kernel/head_64.S
+++ b/arch/x86/kernel/head_64.S
@@ -182,7 +182,7 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL)
/* Enable PAE mode, PSE, PGE and LA57 */
orl $(X86_CR4_PAE | X86_CR4_PSE | X86_CR4_PGE), %ecx
#ifdef CONFIG_X86_5LEVEL
- testl $1, __pgtable_l5_enabled(%rip)
+ testb $1, __pgtable_l5_enabled(%rip)
jz 1f
orl $X86_CR4_LA57, %ecx
1: