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authorLijo Lazar <[email protected]>2022-07-06 13:50:45 +0530
committerAlex Deucher <[email protected]>2023-06-09 09:45:54 -0400
commit7aa8a266aaa25e9e2f85d9d2d594cdff6b5635f2 (patch)
tree51c0d952a648e491e02ff79157f16bb8a61f5be0
parentf8b34a0518701bae8bb02fabe129f01b1dc33336 (diff)
drm/amdgpu: Fix GRBM programming sequence
It needs to be done only for XCC instances in non-AID0. Use the physical instance to determine non-AID0 XCC instances. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Le Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index e9c12b4970f9..43126f7b70ea 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -186,11 +186,14 @@ static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev)
static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev)
{
- int i, num_xcc;
+ int i, num_xcc, dev_inst;
num_xcc = NUM_XCC(adev->gfx.xcc_mask);
- for (i = 2; i < num_xcc; i++)
- WREG32_SOC15(GC, GET_INST(GC, i), regGRBM_MCM_ADDR, 0x4);
+ for (i = 0; i < num_xcc; i++) {
+ dev_inst = GET_INST(GC, i);
+ if (dev_inst >= 2)
+ WREG32_SOC15(GC, dev_inst, regGRBM_MCM_ADDR, 0x4);
+ }
}
static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,