diff options
| author | Tuomas Tynkkynen <[email protected]> | 2015-05-13 17:58:43 +0300 |
|---|---|---|
| committer | Thierry Reding <[email protected]> | 2015-07-16 10:40:20 +0200 |
| commit | 79cf95c763a11d4b365cd5a627fd1ab4dca67890 (patch) | |
| tree | c314059d2be0ef328cb28b533cb2e66fbe414b97 | |
| parent | c38864a703f3fe50e2b87883a0def392dd5bf26f (diff) | |
clk: tegra: Add the DFLL as a possible parent of the cclk_g clock
The DFLL clocksource was missing from the list of possible parents for
the fast CPU cluster. Add it to the list.
Signed-off-by: Tuomas Tynkkynen <[email protected]>
Signed-off-by: Mikko Perttunen <[email protected]>
Acked-by: Michael Turquette <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
| -rw-r--r-- | drivers/clk/tegra/clk-tegra-super-gen4.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-tegra-super-gen4.c b/drivers/clk/tegra/clk-tegra-super-gen4.c index feb3201c85ce..f1f441034b86 100644 --- a/drivers/clk/tegra/clk-tegra-super-gen4.c +++ b/drivers/clk/tegra/clk-tegra-super-gen4.c @@ -44,7 +44,9 @@ static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", "pll_p", "pll_p_out4", "unused", - "unused", "pll_x" }; + "unused", "pll_x", "unused", "unused", + "unused", "unused", "unused", "unused", + "dfllCPU_out" }; static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", "pll_p", "pll_p_out4", "unused", |