diff options
| author | Srinivas Kandagatla <[email protected]> | 2020-12-02 18:07:37 +0000 |
|---|---|---|
| committer | Bjorn Andersson <[email protected]> | 2020-12-28 12:14:23 -0600 |
| commit | 793bbd2db7e35a9dbf006e81a8373cd1c333ae53 (patch) | |
| tree | c6b2f490c27aff0397351c6e5e486bc83e8c7065 | |
| parent | 63e10791ccab664abc031b7fad07674fdae2d829 (diff) | |
arm64: dts: qcom: sm8250: add audio clock controllers
Add audiocc and aoncc clock controller nodes required for audio on RB5.
Signed-off-by: Srinivas Kandagatla <[email protected]>
Tested-by: Dmitry Baryshkov <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[bjorn: Dropped includes for now]
Signed-off-by: Bjorn Andersson <[email protected]>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sm8250.dtsi | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 3aca8d0af97c..98d58943cd05 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1264,6 +1264,26 @@ #hwlock-cells = <1>; }; + audiocc: clock-controller@3300000 { + compatible = "qcom,sm8250-lpass-audiocc"; + reg = <0 0x03300000 0 0x30000>; + #clock-cells = <1>; + clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio", "bus"; + }; + + aoncc: clock-controller@3380000 { + compatible = "qcom,sm8250-lpass-aoncc"; + reg = <0 0x03380000 0 0x40000>; + #clock-cells = <1>; + clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio", "bus"; + }; + gpu: gpu@3d00000 { compatible = "qcom,adreno-650.2", "qcom,adreno"; |