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authorTao Zhou <[email protected]>2020-10-02 11:39:28 -0400
committerAlex Deucher <[email protected]>2020-10-12 14:00:31 -0400
commit771cc67ed08f544ec16d5194e509c66694428e71 (patch)
tree9940edc15bf7da66f5c8b474b8ef92dd484bf39d
parent3e02ad447677b2791af7ae71b29aeb252d680e87 (diff)
drm/amdgpu: add ih ip block for dimgrey_cavefish
Enable ih block for dimgrey_cavefish, same as navy_flounder. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Jiansong Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
-rw-r--r--drivers/gpu/drm/amd/amdgpu/navi10_ih.c1
-rw-r--r--drivers/gpu/drm/amd/amdgpu/nv.c1
2 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index 53ea83c08e8e..837769fcb35b 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -315,6 +315,7 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev)
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
case CHIP_VANGOGH:
+ case CHIP_DIMGREY_CAVEFISH:
ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid);
ih_chicken = REG_SET_FIELD(ih_chicken,
IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1);
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 6c06756a216a..7b261dc44786 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -629,6 +629,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
case CHIP_DIMGREY_CAVEFISH:
amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
break;
default:
return -EINVAL;