aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorSuman Anna <[email protected]>2019-07-22 14:05:38 -0500
committerTero Kristo <[email protected]>2019-08-29 16:04:59 +0300
commit75f535d09735dc815a997b6b61dcd997c5fd3ba1 (patch)
treed09110e2826482519355ba349ef33a7b246baabf
parent2dc61b58efbcc320fce03cdf824404d804c5b31a (diff)
arm64: dts: ti: k3-am65-main: Add hwspinlock node
The Main NavSS block on AM65x SoCs contains a HwSpinlock IP instance that is similar to the IP on some OMAP SoCs. Add the DT node for this on AM65x SoCs. The node is present within the NavSS block, and is added as a child node under the cbass_main_navss interconnect node. Signed-off-by: Suman Anna <[email protected]> Signed-off-by: Tero Kristo <[email protected]>
-rw-r--r--arch/arm64/boot/dts/ti/k3-am65-main.dtsi6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index 12a977f1ab87..9f68ecc8af53 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -413,6 +413,12 @@
ti,sci-rm-range-vint = <0x0>;
ti,sci-rm-range-global-event = <0x1>;
};
+
+ hwspinlock: spinlock@30e00000 {
+ compatible = "ti,am654-hwspinlock";
+ reg = <0x00 0x30e00000 0x00 0x1000>;
+ #hwlock-cells = <1>;
+ };
};
main_gpio0: main_gpio0@600000 {