diff options
| author | Brian Norris <[email protected]> | 2021-09-08 11:13:40 -0700 |
|---|---|---|
| committer | Heiko Stuebner <[email protected]> | 2021-09-20 15:13:24 +0200 |
| commit | 75dccea503b8e176ad044175e891d7bb291b6ba0 (patch) | |
| tree | 34375a4fd49b8568c0a38ccfcc7eeb240d9ba478 | |
| parent | 4b90e34d9a3ba25a62e4ea42d63fbe6c7fb11ed1 (diff) | |
arm64: dts: rockchip: add Coresight debug range for RK3399
Per Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt.
This IP block can be used for sampling the PC of any given CPU, which is
useful in certain panic scenarios where you can't get the CPU to stop
cleanly (e.g., hard lockup).
Reviewed-by: Leo Yan <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Reviewed-by: Douglas Anderson <[email protected]>
Signed-off-by: Brian Norris <[email protected]>
Link: https://lore.kernel.org/r/20210908111337.v2.3.Ibc87b4785709543c998cc852c1edaeb7a08edf5c@changeid
Signed-off-by: Heiko Stuebner <[email protected]>
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3399.dtsi | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 44def886b391..eaf569674db2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -361,6 +361,54 @@ status = "disabled"; }; + debug@fe430000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0 0xfe430000 0 0x1000>; + clocks = <&cru PCLK_COREDBG_L>; + clock-names = "apb_pclk"; + cpu = <&cpu_l0>; + }; + + debug@fe432000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0 0xfe432000 0 0x1000>; + clocks = <&cru PCLK_COREDBG_L>; + clock-names = "apb_pclk"; + cpu = <&cpu_l1>; + }; + + debug@fe434000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0 0xfe434000 0 0x1000>; + clocks = <&cru PCLK_COREDBG_L>; + clock-names = "apb_pclk"; + cpu = <&cpu_l2>; + }; + + debug@fe436000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0 0xfe436000 0 0x1000>; + clocks = <&cru PCLK_COREDBG_L>; + clock-names = "apb_pclk"; + cpu = <&cpu_l3>; + }; + + debug@fe610000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0 0xfe610000 0 0x1000>; + clocks = <&cru PCLK_COREDBG_B>; + clock-names = "apb_pclk"; + cpu = <&cpu_b0>; + }; + + debug@fe710000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0 0xfe710000 0 0x1000>; + clocks = <&cru PCLK_COREDBG_B>; + clock-names = "apb_pclk"; + cpu = <&cpu_b1>; + }; + usbdrd3_0: usb@fe800000 { compatible = "rockchip,rk3399-dwc3"; #address-cells = <2>; |