diff options
| author | Dmytro Laktyushkin <[email protected]> | 2023-05-09 09:38:29 -0400 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2023-06-09 10:42:27 -0400 |
| commit | 75589226372ce5255ffade2ec6dea862338f7595 (patch) | |
| tree | 14c12552071fb0f67edfea1404c545dd058b8dd5 | |
| parent | f36f2648f32c184ffc285a836b1ce3757e966925 (diff) | |
drm/amd/display: disable dcn315 pixel rate crb when scaling
The rough calculation does not account for scaling. Also, make 2
segments the minimum allowed per surface to avoid potential 0 detile
with mpc/odm combine on such outputs.
Reviewed-by: Ariel Bernstein <[email protected]>
Acked-by: Tom Chung <[email protected]>
Signed-off-by: Dmytro Laktyushkin <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c index 42a0157fd813..c6bc2d603ab8 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c @@ -1666,6 +1666,14 @@ static bool allow_pixel_rate_crb(struct dc *dc, struct dc_state *context) if (!res_ctx->pipe_ctx[i].stream) continue; + /*Don't apply if scaling*/ + if (res_ctx->pipe_ctx[i].stream->src.width != res_ctx->pipe_ctx[i].stream->dst.width || + res_ctx->pipe_ctx[i].stream->src.height != res_ctx->pipe_ctx[i].stream->dst.height || + (res_ctx->pipe_ctx[i].top_pipe->plane_state && (res_ctx->pipe_ctx[i].top_pipe->plane_state->src_rect.width + != res_ctx->pipe_ctx[i].top_pipe->plane_state->dst_rect.width || + res_ctx->pipe_ctx[i].top_pipe->plane_state->src_rect.height + != res_ctx->pipe_ctx[i].top_pipe->plane_state->dst_rect.height))) + return false; /*Don't apply if MPO to avoid transition issues*/ if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state != res_ctx->pipe_ctx[i].plane_state) return false; @@ -1715,10 +1723,15 @@ static int dcn315_populate_dml_pipes_from_context( /* Ceil to crb segment size */ int approx_det_segs_required_for_pstate = dcn_get_approx_det_segs_required_for_pstate( &context->bw_ctx.dml.soc, timing->pix_clk_100hz, bpp, DCN3_15_CRB_SEGMENT_SIZE_KB); + if (approx_det_segs_required_for_pstate <= 2 * DCN3_15_MAX_DET_SEGS) { bool split_required = approx_det_segs_required_for_pstate > DCN3_15_MAX_DET_SEGS; split_required = split_required || timing->pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc); split_required = split_required || (pipe->plane_state && pipe->plane_state->src_rect.width > 5120); + + /* Minimum 2 segments to allow mpc/odm combine if its used later */ + if (approx_det_segs_required_for_pstate < 2) + approx_det_segs_required_for_pstate = 2; if (split_required) approx_det_segs_required_for_pstate += approx_det_segs_required_for_pstate % 2; pipes[pipe_cnt].pipe.src.det_size_override = approx_det_segs_required_for_pstate; |