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authorPraveenkumar I <[email protected]>2023-07-13 14:01:01 +0530
committerBjorn Andersson <[email protected]>2023-07-13 21:36:42 -0700
commit752f585805c559e7c990e7d23e49d03167065761 (patch)
treef20afebdc448138e212fb64b907021c8a9388aed
parent4e125191e6cb00d6c3f3a8e1b67fd242e639b3c3 (diff)
arm64: dts: qcom: ipq9574: Add cpu cooling maps
Add cpu cooling maps for passive trip points. The cpu cooling device states are mapped to cpufreq based scaling frequencies. Signed-off-by: Praveenkumar I <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
-rw-r--r--arch/arm64/boot/dts/qcom/ipq9574.dtsi61
1 files changed, 53 insertions, 8 deletions
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 2eadc84fba25..2ba9454ad86e 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&intc>;
@@ -42,6 +43,7 @@
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
cpu-supply = <&ipq9574_s1>;
+ #cooling-cells = <2>;
};
CPU1: cpu@1 {
@@ -54,6 +56,7 @@
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
cpu-supply = <&ipq9574_s1>;
+ #cooling-cells = <2>;
};
CPU2: cpu@2 {
@@ -66,6 +69,7 @@
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
cpu-supply = <&ipq9574_s1>;
+ #cooling-cells = <2>;
};
CPU3: cpu@3 {
@@ -78,6 +82,7 @@
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
cpu-supply = <&ipq9574_s1>;
+ #cooling-cells = <2>;
};
L2_0: l2-cache {
@@ -812,18 +817,28 @@
thermal-sensors = <&tsens 10>;
trips {
- cpu-critical {
+ cpu0_crit: cpu-critical {
temperature = <120000>;
hysteresis = <10000>;
type = "critical";
};
- cpu-passive {
+ cpu0_alert: cpu-passive {
temperature = <110000>;
hysteresis = <1000>;
type = "passive";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu0_alert>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu1-thermal {
@@ -832,18 +847,28 @@
thermal-sensors = <&tsens 11>;
trips {
- cpu-critical {
+ cpu1_crit: cpu-critical {
temperature = <120000>;
hysteresis = <10000>;
type = "critical";
};
- cpu-passive {
+ cpu1_alert: cpu-passive {
temperature = <110000>;
hysteresis = <1000>;
type = "passive";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu1_alert>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu2-thermal {
@@ -852,18 +877,28 @@
thermal-sensors = <&tsens 12>;
trips {
- cpu-critical {
+ cpu2_crit: cpu-critical {
temperature = <120000>;
hysteresis = <10000>;
type = "critical";
};
- cpu-passive {
+ cpu2_alert: cpu-passive {
temperature = <110000>;
hysteresis = <1000>;
type = "passive";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu2_alert>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu3-thermal {
@@ -872,18 +907,28 @@
thermal-sensors = <&tsens 13>;
trips {
- cpu-critical {
+ cpu3_crit: cpu-critical {
temperature = <120000>;
hysteresis = <10000>;
type = "critical";
};
- cpu-passive {
+ cpu3_alert: cpu-passive {
temperature = <110000>;
hysteresis = <1000>;
type = "passive";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu3_alert>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
wcss-phyb-thermal {