diff options
| author | Siddharth Vadapalli <[email protected]> | 2023-03-15 14:54:08 +0530 |
|---|---|---|
| committer | Vinod Koul <[email protected]> | 2023-04-12 22:08:00 +0530 |
| commit | 73b46467cac027fe6cbe6585946726b53b80bfdb (patch) | |
| tree | 78ee5f825a38134831f6b1fb3a118765059d4441 | |
| parent | 57c0e1362fdd57d0cea7ab1e583b58abf4bd8c2d (diff) | |
dt-bindings: phy: ti: phy-gmii-sel: Add support for J784S4 CPSW9G
The CPSW9G instance of CPSW Ethernet Switch on TI's J784S4 SoC supports
additional PHY modes like QSGMII. Add a compatible for it.
Enable the use of "ti,qsgmii-main-ports" property for J784S4 CPSW9G.
Signed-off-by: Siddharth Vadapalli <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
| -rw-r--r-- | Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml index 3699a06bdf6e..be41b4547ec6 100644 --- a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml +++ b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml @@ -55,6 +55,7 @@ properties: - ti,am654-phy-gmii-sel - ti,j7200-cpsw5g-phy-gmii-sel - ti,j721e-cpsw9g-phy-gmii-sel + - ti,j784s4-cpsw9g-phy-gmii-sel reg: maxItems: 1 @@ -87,6 +88,7 @@ allOf: - ti,am654-phy-gmii-sel - ti,j7200-cpsw5g-phy-gmii-sel - ti,j721e-cpsw9g-phy-gmii-sel + - ti,j784s4-cpsw9g-phy-gmii-sel then: properties: '#phy-cells': @@ -113,6 +115,7 @@ allOf: contains: enum: - ti,j721e-cpsw9g-phy-gmii-sel + - ti,j784s4-cpsw9g-phy-gmii-sel then: properties: ti,qsgmii-main-ports: @@ -130,6 +133,7 @@ allOf: enum: - ti,j7200-cpsw5g-phy-gmii-sel - ti,j721e-cpsw9g-phy-gmii-sel + - ti,j784s4-cpsw9g-phy-gmii-sel then: properties: ti,qsgmii-main-ports: false |