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authorLinus Walleij <[email protected]>2022-08-15 21:34:40 +0200
committerLinus Walleij <[email protected]>2022-10-17 15:05:52 +0200
commit7341b2c1b9c8997ffb87b5bfdb8feaf02b52d8bf (patch)
tree9e74d1e760286ed8a5746279ca58994adb93c43e
parent7b7c66ec81d80581939d3d774491acd761808f20 (diff)
ARM: dts: ux500: Fix up the Janice NFC chip
The NFC chip in Janice is a PNX544 not PNX547 and it is on I2C address 0x2b. Fix it up. This is only mounted in Janice models designated GT-I9070P. Cc: Stefan Hansson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
-rw-r--r--arch/arm/boot/dts/ste-ux500-samsung-janice.dts14
1 files changed, 9 insertions, 5 deletions
diff --git a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts
index b34bd19ad815..04cd3c3757d6 100644
--- a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts
+++ b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts
@@ -365,9 +365,13 @@
#address-cells = <1>;
#size-cells = <0>;
- nfc@30 {
- compatible = "nxp,pn547", "nxp,nxp-nci-i2c";
- reg = <0x30>;
+ /* This is only mounted on the GT-I9070P */
+ nfc@2b { /* 0x30? */
+ /* NXP NFC circuit PN544 C1 marked NXP 44501 */
+ compatible = "nxp,pn544-i2c";
+ /* IF0, IF1 high, gives I2C address 0x2B */
+ reg = <0x2b>;
+ clock-frequency = <400000>;
/* NFC IRQ on GPIO32 */
interrupt-parent = <&gpio1>;
interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
@@ -376,7 +380,7 @@
/* GPIO88 */
enable-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
- pinctrl-0 = <&pn547_janice_default>;
+ pinctrl-0 = <&pn544_janice_default>;
};
};
@@ -951,7 +955,7 @@
};
};
nfc {
- pn547_janice_default: pn547_janice {
+ pn544_janice_default: pn544_janice {
/* Interrupt line */
janice_cfg1 {
pins = "GPIO32_V2";