diff options
| author | Sibi Sankar <quic_sibis@quicinc.com> | 2024-06-12 18:10:52 +0530 |
|---|---|---|
| committer | Jassi Brar <jassisinghbrar@gmail.com> | 2024-07-10 13:24:55 -0500 |
| commit | 6e7c4cc55dbc461c08e00f0ef16867fe6bf014aa (patch) | |
| tree | c5e1d34cf0ae76db4e22894bb3aa2f452698419e | |
| parent | af5da7b0944c3616fa6add186043637092d94200 (diff) | |
dt-bindings: mailbox: qcom: Add CPUCP mailbox controller bindings
Add devicetree binding for CPUSS Control Processor (CPUCP) mailbox
controller.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
| -rw-r--r-- | Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml new file mode 100644 index 000000000000..f7342d04beec --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/qcom,cpucp-mbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. CPUCP Mailbox Controller + +maintainers: + - Sibi Sankar <quic_sibis@quicinc.com> + +description: + The CPUSS Control Processor (CPUCP) mailbox controller enables communication + between AP and CPUCP by acting as a doorbell between them. + +properties: + compatible: + items: + - const: qcom,x1e80100-cpucp-mbox + + reg: + items: + - description: CPUCP rx register region + - description: CPUCP tx register region + + interrupts: + maxItems: 1 + + "#mbox-cells": + const: 1 + +required: + - compatible + - reg + - interrupts + - "#mbox-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + mailbox@17430000 { + compatible = "qcom,x1e80100-cpucp-mbox"; + reg = <0x17430000 0x10000>, <0x18830000 0x10000>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <1>; + }; |