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authorVedant Deshpande <[email protected]>2024-08-16 18:43:48 +0000
committerThierry Reding <[email protected]>2024-08-29 17:32:16 +0200
commit6e1a196425fcd50d7d29fe7eb36f2fe2da8e0018 (patch)
tree002834497366c7cdf2e939fb842b634dd15f7d60
parent0580286d0d22e6508701dff1397bb7e66386c359 (diff)
arm64: tegra: Add p3767 PCIe C4 EP details
Add implementation details for Orin NX/Nano PCIe EP on C4. Signed-off-by: Vedant Deshpande <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767.dtsi12
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767.dtsi
index 81d4f4f12ab1..19340d13f789 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767.dtsi
@@ -186,6 +186,18 @@
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
};
+ pcie-ep@14160000 {/* C4 - End Point */
+ phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,
+ <&p2u_hsio_7>;
+ phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
+ reset-gpios = <&gpio
+ TEGRA234_MAIN_GPIO(L, 1)
+ GPIO_ACTIVE_LOW>;
+ nvidia,refclk-select-gpios = <&gpio_aon
+ TEGRA234_AON_GPIO(AA, 4)
+ GPIO_ACTIVE_HIGH>;
+ };
+
/* C7 - M.2 Key-M */
pcie@141e0000 {
status = "okay";