diff options
| author | Marc Zyngier <[email protected]> | 2023-08-15 19:38:37 +0100 |
|---|---|---|
| committer | Marc Zyngier <[email protected]> | 2023-08-17 10:00:26 +0100 |
| commit | 6ddea24dfd59f0fc78a87df54d428e3a6cf3e11f (patch) | |
| tree | e33e585529ebe6d0a83a73fd25c5559dcf533b0c | |
| parent | 464f2164da7e4cb50faec9d56226b22c9b36cdda (diff) | |
arm64: Add missing DC ZVA/GVA/GZVA encodings
Add the missing DC *VA encodings.
Reviewed-by: Eric Auger <[email protected]>
Reviewed-by: Miguel Luis <[email protected]>
Acked-by: Catalin Marinas <[email protected]>
Reviewed-by: Zenghui Yu <[email protected]>
Reviewed-by: Jing Zhang <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
| -rw-r--r-- | arch/arm64/include/asm/sysreg.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index ed2739897859..5084add86897 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -150,6 +150,11 @@ #define SYS_DC_CIGVAC sys_insn(1, 3, 7, 14, 3) #define SYS_DC_CIGDVAC sys_insn(1, 3, 7, 14, 5) +/* Data cache zero operations */ +#define SYS_DC_ZVA sys_insn(1, 3, 7, 4, 1) +#define SYS_DC_GVA sys_insn(1, 3, 7, 4, 3) +#define SYS_DC_GZVA sys_insn(1, 3, 7, 4, 4) + /* * Automatically generated definitions for system registers, the * manual encodings below are in the process of being converted to |