diff options
| author | Arnd Bergmann <[email protected]> | 2020-07-22 21:51:57 +0200 |
|---|---|---|
| committer | Arnd Bergmann <[email protected]> | 2020-07-22 21:51:57 +0200 |
| commit | 6ce448eeef446d212c0d6c5d1affd42cf591ed36 (patch) | |
| tree | 200318c354f48465ad758576d3d70539e7cec6a5 | |
| parent | 4828f4570873be48c4007634091b3bd8a59bb7ad (diff) | |
| parent | 5720fcdc2e5af74e51c5e3102fcefd9fb061a666 (diff) | |
Merge tag 'hisi-arm32-dt-for-5.9' of git://github.com/hisilicon/linux-hisi into arm/dt
ARM: DT: Hisilicon ARM32 SoCs updates for v5.9
- Update L2 cache controller nodes to fix dtschema validator warnings
for hi3620 and hix5hd2
* tag 'hisi-arm32-dt-for-5.9' of git://github.com/hisilicon/linux-hisi:
ARM: dts: hisilicon: Align L2 cache-controller nodename with dtschema
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Arnd Bergmann <[email protected]>
| -rw-r--r-- | arch/arm/boot/dts/hi3620.dtsi | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/hisi-x5hd2.dtsi | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi index 9c207a690df5..f0af1bf2b4d8 100644 --- a/arch/arm/boot/dts/hi3620.dtsi +++ b/arch/arm/boot/dts/hi3620.dtsi @@ -71,7 +71,7 @@ interrupt-parent = <&gic>; ranges = <0 0xfc000000 0x2000000>; - L2: l2-cache { + L2: cache-controller { compatible = "arm,pl310-cache"; reg = <0x100000 0x100000>; interrupts = <0 15 4>; diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi index 696e6982a688..3ee7967c202d 100644 --- a/arch/arm/boot/dts/hisi-x5hd2.dtsi +++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi @@ -381,7 +381,7 @@ interrupts = <1 13 0xf01>; }; - l2: l2-cache { + l2: cache-controller { compatible = "arm,pl310-cache"; reg = <0x00a10000 0x100000>; interrupts = <0 15 4>; |